1. Field of the Invention
The present invention relates to a cache control device, and more particularly to a cache control device to be used as a set associative cache control device.
2. Description of the Prior Art
It is a well-known fact that in recent years the operating frequency of a general-purpose microcomputer or a digital signal processor (hereinafter, referred to as DSP for short) is made higher and cache devices to be used in them are also made higher in their operating frequency.
It is also a well-known fact that in recent years, among the cache devices described above, a set associative cache device which is used particularly for improving the hit rate of a cache attracts people""s attention. Such a conventional cache device is disclosed for example in Japanese Patent Laid-Open Publication No.H8-263370.
The set associative cache device has a higher hit rate in comparison with a direct mapped cache device having the same capacity.
And with the advance of micro-fabrication in a state-of-the-art semiconductor manufacturing process the difference between the speed of a bus in an external storage used in a general-purpose microcomputer or a DSP and the operating speed inside a processor is only more increased. That is to say, the hit rate of a cache memory inside a processor has had a larger influence on performance of the whole processor.
It is expected that after now in order to improve the hit rate of a cache a cache device adopts more frequently a set associative method than a direct mapped method. Furthermore, measures for low power consumption are more intensely demanded in order to adopt a cache device as a processor intended for a portable terminal.
A set associative cache of the prior art is also well known which compares first a way 0 for example and, when no coincidence is encountered, compares the remaining ways instead of simultaneously comparing ways of a set associative cache device in order to meet this demand.
The composition of a set associative cache device of the prior art is shown in FIG. 1 and the timing chart of its operation is shown in FIG. 2.
Referring to FIG. 1, the value of an address bus 80 to be inputted into each of caches (21a, 22a, 23a and 24a) of a set associative cache device of the prior art is not yet defined before the comparing operation of caches, and a selector 82 selects the value of an address bus 1 or the value of an address bus 2.
Due to this, when the comparison of way 0 results in no coincidence, after a miss-hit signal 16 is generated the selector 82 inputs the next address as a signal 80 into ways 1 way to 3. And the address 80 to be inputted into the caches is generated at time t3 in FIG. 2.
However, the above-mentioned cache control device of the prior art has a disadvantage that generation of an address 80 to be inputted into a cache at time t3 in FIG. 2 is delayed and therefore comes to make slower the operating speed of the cache.
A main object of the present invention is to provide a high-speed cache device being a set associative cache device haying ways which are not simultaneously confirmed with regard to coincidence, the set associative cache device adopting a method of selecting in advance an address to be inputted into the cache RAM of each way prior to comparison of each way instead of a method of selecting the address on the basis of a miss-hit signal generated from a result of comparison of a way.
A first cache control device of the present invention comprises;
a first register having a first address bus connected to its input side, having a second address bus connected to its output side, and being driven by a clock signal,
a second register having the second address bus connected to its input side and a third address bus connected to its output side, and being driven by a clock signal,
a first cache having the first address bus connected to its input side,
a second cache each having the second address bus connected to its input side,
a first comparator for comparing the output of the second address bus with the output of the first cache,
a second comparator for comparing the output of the third address bus with the outputs of the second caches,
a first multiplexer for selecting data of the first comparator or the second comparators,
a second multiplexer for selecting data of the first cache or the second caches, and
an access controller for controlling the first and second caches,
the cache control device selecting in advance the first to third address buses prior to comparing the output of the second address bus with the output of the first cache and comparing the output of the third address bus with the outputs of the second caches.
And a second cache control device of the present invention comprises;
a first register having a first address bus connected to its input side, having a second address bus connected to its output side, and being driven by a clock signal,
a second register having the second address bus connected to its input side, having a third address bus connected to its output side, and being driven by a clock signal,
a third register having the third address bus connected to its input side, having a fourth address bus connected to its output side, and being driven by a clock signal,
a first cache having the first address bus connected to its input side,
a second cache having the second address bus connected to its input side,
a third caches each having the third address bus connected to its input side,
a first comparator for comparing the output of the second address bus with the output of the first cache,
a second comparator for comparing the output of the third address bus with the output of the second cache,
a third comparators for comparing the output of the fourth address bus with the outputs of the third caches,
a first multiplexer for selecting data of the first or second comparator, or the third comparators,
a second multiplexer for selecting data of the first or second cache, or the third caches, and
an access controller for controlling the first, second and third caches,
the cache control device selecting in advance the first to fourth address buses prior to comparing the output of the second address bus with the output of the first cache, comparing the output of the third address bus with the output of the second cache and comparing the output of the fourth address bus with the outputs of the third caches.
Further, a cache control device of the present invention adopts various preferred application forms as described below.
That is to say, a cache control device of the present invention is a set associative cache device.
And the first cache of a cache control device of the present invention has a first tag RAM for receiving the first address data, and the second cache has a second tag RAM for receiving the second address data.
And the first and second caches of a cache control device of the present invention each have a data RAM controlled by the access controller.
And the first comparator of a cache control device of the present invention compares the output of the second address bus with the output of the first tag RAM, and the second comparators compare the output of the third address bus with the outputs of the second tag RAMs.
And a cache control device of the present invention has the caches of five or more in number, or the cache control device has the comparators of five or more in number.